The present invention relates to a wiring substrate, a semiconductor device, and a method for manufacturing the wiring substrate.
When mounting a component such as a semiconductor chip on a wiring substrate, an insulating material referred to as a solder resist is applied to the outermost layer of the wiring substrate to protect the wiring substrate from solder, contamination, and the like. In this case, an opening for exposing a wiring layer under the solder resist is formed in the wiring substrate to form a coupling pad (e.g., flip-chip pad) that is necessary for coupling with the mounting component. Photolithography, for example, is performed to form the opening.
Referring to FIG. 1A, a core substrate 60 is first prepared. Then, the required number of wiring layers 61 and 62 and insulative layers 63 and 64, which respectively cover the wiring layers 61 and 62 are formed on a core substrate 60. A wiring layer 65, which serves as an uppermost layer, and an insulative layer (solder resist layer 66), which covers the wiring layer 65, are then formed. Photolithography is performed to expose and develop the solder resist layer 66. As shown in FIG. 1B, this forms openings 66X of a predetermined pattern. The openings 66X expose parts of the wiring layer 65 in the uppermost layer as coupling pads 65a. In this manner, the pads 65a are formed by openings in the solder resist layer 66.
Japanese Laid-Open Patent Publication No. 2002-246756 describes an example of the above-described prior art.
Due to the increasing scale of integration in semiconductor chips, the number of coupling terminals in a semiconductor chip that is connected to a wiring substrate is increasing, that is, the number of pins is increasing. (greater number of pins). Further, the pitch between coupling terminals in a semiconductor chip has become narrower. Accordingly, miniaturization of a pad structure of a wiring substrate has become necessary. In particular, a higher wire density is required in the uppermost layer of a wiring substrate. To increase the wire density, it is significant that the regions of the wiring layer 65 arranged between the pads 65a be as large as possible.
As shown in the perspective view of FIG. 2, the wiring layer 65 in the uppermost layer of the wiring substrate includes lands L, each having a larger diameter than the openings 66X. This obtains each pad 65a with a desired diameter without the corresponding opening 66X (refer to broken line) of the solder resist layer 66 being separated from the wiring layer 65. As shown in FIG. 3B, such a land L is formed in the same manner regardless of whether a via 67, which electrically connects the corresponding pad 65a to the inner wiring layer 62, is arranged directly below the pad 65a (refer to left side in FIG. 3B) or whether the via 67 is separated from the corresponding pad 65a and located below a part of the wiring layer 65 extended outward from the pad 65a (refer to right side in FIG. 3B). Thus, as shown in FIG. 3A, each pad 65a includes a land L having a diameter D2 that is greater than a diameter D1 of the pad 65a. Accordingly, the lands L decrease the width WB of the region in which the wiring layer 65 can be arranged between pads 65a. Thus, the wire density cannot be increased.